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 FCT520.pm6
32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520T/2520T PI29FCT521T
Fast CMOS Multilevel Pipeline Registers
Product Features:
* PI29FCT520T and PI29FCT521T are pinout and function compatible with IDT29FCT520/521, QS29FCT520/521 and AMD's Am29520/521 * Four 8-bit high-speed registers * Hold, Transfer, and load instructions * Dual two-level or single four-level pipeline operation * TTL input and output levels, reducing problematic "ground bounce" * High output drive IOL = 48 mA * Extremely low static power (1 mW, typ.) * Industrial operating temperature range: -40C to +85C * FCT (2xxxT) has a 25 series resistor. * Packages available: - 24-pin 300 mil wide plastic DIP (P24) - 24-pin 150 mil wide plastic QSOP (Q24) - 24-pin 150 mil wide plastic TQSOP (R24) - 24-pin 300 mil wide plastic SOIC (S24)
Product Description:
Pericom Semiconductor's PI29FCT series of logic circuits are pro-duced in the Company's advanced 0.8 micron CMOS technology, achieving industry leading speed grades. The PI29FCT520T/2520T and PI29FCT521T are multilevel pipeline registers containing four 8-bit positive triggered registers which can be configured as a dual 2-level or a single 4-level pipeline. These products are designed for use as temporary storage or for storage delays in pipelined systems. The PI29FCT521T differs from the PI29FCT520T/2520T only in the way data is loaded into and between registers in the dual 2-level operation. When data is entered into the first level (I = 2 or I = 1) of the PI29FCT520T/2520T, the existing data in the first level is moved to the second level. In the PI29FCT521T, these instructions simply overwrite the data in the first level. Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0) causing the first level to change. In either part, I = 3 shift instruction puts the registers on hold. Device models available upon request.
Logic Block Diagram
D0-D7 8
MUX 2 I0,I1 REGISTER CONTROL 1 CLK OCTAL REGISTER A1 OCTAL REGISTER B1
OCTAL REGISTER A2
OCTAL REGISTER B2
S0,S1
2 MUX
OE 8
Y0-Y7
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PI29FCT520/521T/2520T MULTILEVEL PIPELINE REGISTERS
Product Pin Configuration
I0 I1 D0 D1 D2 D3 D4 D5 D6 D7 CLK GND
Product Pin Description
Pin Name Description Output Enable Input (Active LOW) for 3-State Output Port Clock Input. Enter data into registers on LOW-to-HIGH transistions Instruction Inputs Multiplexer Select. Inputs either register A1, A2, B1, or B2 data to be avaialbe at the output ports Register Inputs Register Outputs Ground Power
VCC S0 S1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 OE
1 24 2 23 3 22 4 21 5 24-PIN 20 P24 6 19 Q24 18 7 R24 8 17 S24 9 16 10 15 11 14 12 13
OE CLK I0,I1 S0,S1
Dx Yx GND VCC
Register Selection
S1 0 0 1 1 S0 0 1 0 1 Register B2 B1 A2 A1
PI29FCT520/T2520T Data Loading
DUAL 2-LEVEL SINGLE 4-LEVEL
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
I=2 NOTE: I = 3 FOR HOLD
I=1
I=0
PI29FCT521T Data Loading
DUAL 2-LEVEL SINGLE 4-LEVEL
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
I=2 NOTE: I = 3 FOR HOLD
I=1
I=0
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FCT520.pm6
32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520/521T/2520T MULTILEVEL PIPELINE REGISTERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................................. -55C to +125C Ambient Temperature with Power Applied ................................. -40C to +85C Supply Voltage to Ground Potential (Inputs & Vcc Only) .......... -0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) ....... -0.5V to +7.0V DC Input Voltage ......................................................................... -0.5V to +7.0V DC Output Current ................................................................................... 120 mA Power Dissipation ......................................................................................... 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 5V 5%)
Parameters VOH VOL VIH VIL IIH IIL IOZH IOZL VIK IOS IOFF VH Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current High Impedance Output Current Clamp Diode Voltage Short Circuit Current Power Down Disable Input Hysteresis VCC = MIN., IIN = -18 mA VCC = MAX. , VOUT = GND VCC = GND, VOUT = 4.5V
(3)
Test Conditions(1) VCC = MIN., VIN = VIH VCC = MIN., VIN = VIH
OR
Min. 2.4
Typ(2) 3.0 0.3 0.3
Max.
Units V
VIL VIL
IOH = -15.0 mA IOL = 48 mA
0.50 0.50
V V V
OR
IOL = 12 mA (25 series) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = MAX. VCC = MAX. VCC = MAX. VIN = VCC VIN = GND VOUT = 2.7V VOUT = 0.5V 2.0
0.8 1 -1 1 -1 -0.7 -60 -- -120 -- 200 100 -1.2
V A A A A V mA A mV
Capacitance (TA = 25C, f = 1 MHz)
Parameters(4) CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Typ 6 8 Max. 10 12 Units pF pF
Notes: 1. For conditions show as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested.
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32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520/521T/2520T MULTILEVEL PIPELINE REGISTERS
Power Supply Characteristics
Parameters Description ICC
ICC
Test Conditions(1) VCC = Max. VCC = Max. VCC = Max., Outputs Open OE = GND One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = GND One Bit Toggling fI = 5 MH 50% Duty Cycle VCC = Max., Outputs Open fCP = 10 MHZ 50% Duty Cycle OE = GND Eight Bits Toggling fI = 5 MHz 50% Duty Cycle VIN = GND or VCC VIN = 3.4V(3) VIN = GND VIN = VCC
Min.
Typ(2) 0.1 0.5 0.15
Max. 10 2.0 0.25
Units A mA mA/ MHz
Quiescent Power Supply Current Supply Current per Input @ TTL HIGH Supply Current per Input per MHz(4)
ICCD
IC
Total Power Supply Current(5)
VIN = GND VIN = VCC
1.5
3.5(5)
mA
VIN = 3.4V VIN = GND
2.0
5.5(5)
VIN = GND VIN = VCC
3.8
7.3(5)
VIN = 3.4V VIN = GND
6.0
16.3(5)
Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V, control inputs only); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply characteristics. 5. Values for these conditions are examples of the ICC formula. These limits are guAranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz.
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FCT520.pm6
32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 32109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI29FCT520/521T/2520T MULTILEVEL PIPELINE REGISTERS
PI29FCT520T/2520T Switching Characteristics over Operating Range
FCT520AT/2520AT FCT520BT/2520BT Com. Com. Max Min Max Unit
Parameters tPLH tPHL tPLH tPHL tSU tH tSU tH tPZH tPZL tPHZ tPLZ tW
Description Propagation Delay CLK to YX Propagation Delay S0 or S1 to YX Setup Time HIGH or LOW DX to CLK Hold Time HIGH or LOW DX to CLK Setup Time HIGH or LOW I0 or I1 to CLK Hold Time HIGH or LOW I0 or I1 to CLK Output Enable Time OE to YX Output Disable Time(3) OE to Yx Clock Pulse Width(3) HIGH or LOW
Conditions(1) CL = 50 pF RL = 500
Min
2.0 2.0 5.0 2.0 5.0 2.0 1.5 1.5 7.0
14.0 13.0 -- -- -- -- 12.0 15.0 --
2.0 2.0 2.5 2.0 4.0 2.0 1.5 1.5 5.5
7.5 7.5 -- -- -- -- 7.0 7.5 --
ns ns ns ns ns ns ns ns ns
PI29FCT521T Switching Characteristics over Operating Range
FCT521AT Com. FCT521BT Com. Max Min Max Unit
Parameters tPLH tPHL tPLH tPHL tSU tH tSU tH tPZH tPZL tPHZ tPLZ tW
Description Propagation Delay CLK to YX Propagation Delay S0 or S1 to YX Setup Time HIGH or LOW DX to CLK Hold Time HIGH or LOW DX to CLK Setup Time HIGH or LOW I0 or I1 to CLK Hold Time HIGH or LOW I0 or I1 to CLK Output Enable Time OE to Yx Output Disable Time(3) OE to Yx Clock Pulse Width(3) HIGH or LOW
Conditions (1) CL = 50 pF RL = 500
Min
2.0 2.0 5.0 2.0 5.0 2.0 1.5 1.5 7.0
14.0 13.0 -- -- -- -- 12.0 15.0 --
2.0 2.0 2.5 2.0 4.0 2.0 1.5 1.5 5.5
7.5 7.5 -- -- -- -- 7.0 7.5 --
ns ns ns ns ns ns ns ns ns
Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not production tested. Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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